1. Field of the Invention
The present invention generally relates to a manufacturing technique for a wiring substrate on which a semiconductor chip is mounted. Particularly, this invention relates to “semiconductor-chip-mounting” wiring substrate having position information and a semiconductor device using the same wherein failure analysis can be effectively conducted when a defect occurs in the wiring substrate or the semiconductor device using the same. This invention also relates to a process for manufacturing such a semiconductor-chip-mounting wiring substrate and a semiconductor device using the same.
2. Description of the Related Art
Recently, there has been a demand for reducing the weight and thickness of a wiring substrate so that a BGA (Ball Grid Array) semiconductor chip, the size of which is reduced and the number of pins of which is increased, can be mounted on the wiring substrate. Therefore, a plastic type wiring substrate, in which glass-epoxy resin composite boards are laminated, is widely used for the wiring substrate. This plastic type wiring board is typically manufactured as follows. A resin board (glass-epoxy resin composite board), on one face or both faces of which copper foil is stuck, is subjected to resist coating and etching so that a copper wiring pattern is formed on the board. Alternatively, through-holes are formed on a resin board and copper plating is conducted on the inner wall faces of the through-holes. Such resin boards are laminated with epoxy adhesive to obtain a plastic type wiring board. A predetermined number of semiconductor chips are mounted on the thus made wiring substrate. In this way, a semiconductor device is manufactured.
In general, the manufacturing process of this semiconductor device includes: a process of die attaching for mounting semiconductor chips on the substrate; a process of wire bonding for electrically connecting electrodes of each semiconductor chip with a wiring pattern on the substrate; a process of molding for sealing the semiconductor chips and wires with sealing resin; a process of ball mounting for connecting external connecting terminals such as solder balls with a substrate face on a side opposite to the side on which the semiconductor chips are mounted; and a cutting process for cutting the substrate into packages (semiconductor device). Concerning the method of molding, there are provided an individual molding in which molding is conducted for each semiconductor chip and a batch type molding in which molding is conducted for a plurality of semiconductor chips all at once. Recently, there is a tendency toward the batch type molding from the viewpoint of enhancing the efficiency of assembling a package.
If the semiconductor device manufactured by this manufacturing process is evaluated, its performance, price and reliability are important factors. Because the semiconductor device has been highly integrated and further the manufacturing device has been highly developed recently, the performance of the semiconductor device is greatly enhanced and the price is greatly reduced. Since the performance and price are stabilized as described above, in order to enhance the reliability, it is very important to quickly conduct failure analysis at a high technical level.
According to the prior art, for example, failure analysis is conducted as follows. After the electrical characteristic evaluation is completed for each semiconductor device which has already been subjected to the diffusion process at the wafer level, each semiconductor device is sorted so as to determine whether it is a non-defective product or it is a defective product. When a defective product is found, it is subjected to the failure analysis, so that the cause of the failure can be found. On the other hand, a non-defective product is subjected to mounting, and a delivery inspection is made to find whether it is a non-defective product or it is a defective product. When the semiconductor device is a non-defective product, it is delivered to the market. When the semiconductor device is a defective product, failure analysis is conducted in the same manner as that described before, so that the cause of the failure can be found. Further, when the non-defective product (semiconductor device), which has already been delivered to the market, becomes defective, the defective semiconductor device is recalled and subjected to failure analysis in the same manner so as to find the cause of the failure.
However, the following problems may be encountered in the aforementioned conventional method of failure analysis for analyzing a failure of a semiconductor device. In the case where a problem is found in a semiconductor device by a delivery inspection conducted after the product has been assembled (after it has been divided into each package), it is impossible to clearly specify a position of the semiconductor device at which the package (semiconductor device) was located on a sheet which is a state of the wiring substrate before it was divided into each package. Specifically, it is impossible to clearly judge whether the problems were caused at the specific position on the wiring substrate or the problems were caused in a specific process in the manufacturing process.
In order to make sure where each package was located when it was in a sheet state, it was necessary to make a reproducing experiment in such a manner that marking such as scratching, was manually conducted in the sheet state so that each package position can be specified after the completion of assembling a product.
However, this work is very complicated and takes a long time. Therefore, from the viewpoint of enhancing the efficiency of a failure analysis, it is not necessarily preferable to conduct marking and make such a reproducing experiment. Further, even if the above reproducing experiment is made, it is sometimes difficult to make sure of the position of each package.
As described above, according to the prior art, in the case where some problems occur in the delivery inspection, it is not always possible to clearly specify the position of each package (semiconductor device) when it was in a sheet state. Therefore, it was impossible to quickly feed back the result of the failure analysis to the manufacturing process. Accordingly, it was impossible to enhance the efficiency of the failure analysis. The above problems may also occur in the case where a semiconductor device, which was once delivered to the market, becomes defective.
In order to solve the above problems, it is possible to take a countermeasure in which a piece of characteristic information is given to each semiconductor chip in the manufacturing process. An example of this countermeasure is disclosed in Japanese Unexamined Patent Publication No. (JP-A) 5-129384. According to the above patent publication, numerals or marks representing a piece of chip attribute information, which represents a position on a wafer at which the chip was located in the manufacturing process, are written in the periphery of a semiconductor element mounting region on the wafer, which is a region finally cut off as an individual semiconductor chip, except for a region in which the semiconductor circuit is formed.
However, according to the above technique described in JP-A 5-129384, since the chip attribute information is composed of numerals or marks which are combined with each other, it is necessary to provide a region on the wafer in which the chip attribute information is written. Since the space on the wafer is limited, it is difficult to write the chip attribute information on the wafer. Further, this technique disclosed in JP-A 5-129384 is provided for discriminating not a package substrate but a wafer.
Separately from the technique disclosed in the above patent publication, it is possible to consider a technique in which the same chip attribute information is written on the connecting ball joining face of the wafer which is opposite to the side on which the chip is mounted.
However, according to this method, there will be a case in which it is impossible to write the chip attribute information because the space is limited depending upon an arrangement and an arrangement pitch of external terminals (solder balls) to be joined since a demand for reducing the size and increasing the number of pins is strong.